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| TECHNICAL DATA SL74LV00 Quad 2-Input NAND Gate The SL74LV00 is low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT00A. The SL74LV00 provides the 2-Input NAND function. * * * Optimized for Low Voltage applications: 1.2 to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Low Input Current ORDERING INFORMATION SL74LV00N Plastic SL74LV00D SOIC TA = -40 / 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM 01 02 04 05 09 10 12 13 1A 1B 2A 2B 3A 3B 4A 4B 2Y 1Y 03 06 3Y 08 FUNCTION TABLE 4Y 11 A L PIN 14 =VCC PIN 7 = GND L H H H - high level L - low level Input B L H L H Y Output =A H H H L *B SLS System Logic Semiconductor 1 SL74LV00 MAXIMUM RATINGS * Symbol VCC IIK * 1 2 Parameter DC supply voltage (Referenced to GND) DC input diode current DC output diode current DC output source or sink current -bus driver outputs DC VCC current for types with - bus driver outputs DC GND current for types with - bus driver outputs Power dissipation per package, plastic DIP+ SOIC package+ Storage temperature Lead temperature, 1.5 mm from Case for 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package) Value -0.5 / +5.0 20 50 25 50 50 750 500 -65 / +150 260 Unit V mA mA mA mA mA mW C C IOK * IO * ICC IGND PD 3 Tstg TL * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/C from 70 to 125C SOIC Package: : - 8 mW/C from 70 to 125C * 1: VI < -0.5 or VI > VCC+0.5V * 2: Vo < -0.5 or Vo > VCC+0.5V * 3: -0.5V < Vo < VCC+0.5V RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V Min 1.2 0 -40 0 0 0 0 Max 3.6 VCC +125 1000 700 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor 2 SL74LV00 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditions VCC, V 25C min VIH High-Level Input Voltage 1.2 2.0 3.0 3.6 1.2 2.0 3.0 3.6 1.2 2.0 3.0 3.6 3.0 1.2 2.0 3.0 3.6 3.0 3.6 3.6 3.6 0.9 1.4 2.1 2.5 1.1 1.92 2.92 3.52 2.48 max 0.3 0.6 0.9 1.1 0.09 0.09 0.09 0.09 0.33 -0.1 0.1 2.0 Guaranteed Limit -40C / 85C min 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.34 max 0.3 0.6 0.9 1.1 0.1 0.1 0.1 0.1 0.4 -1.0 1.0 20 -40C / 125C min 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.20 max 0.3 0.6 0.9 1.1 0.1 0.1 0.1 0.1 0.5 -1.0 1.0 40 V Unit VIL Low -Level Input Voltage V VOH High-Level Output VI = VIL or VIH Voltage IO = -50 A V VI = VIL or VIH IO = -6.0 mA VOL Low-Level Output VI = VIL or VIH Voltage IO = 50 A V V VI = VIL or VIH IO = 6.0 mA IIL III INN Low-Level Input Leakage Current VI = 0 V V A A A High-Level Input VI = VCC Leakage Current Quiescent Supply VI = 0 A or VCC Current IO = 0 A (per Package) SLS System Logic Semiconductor 3 SL74LV00 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t LH = t HL = 6.0 ns, VIL=0V, VIH=VCC) Symbol Parameter VCC V min tTHL, (t TLH) Output Transition Time, Any Output (Figure 1) Propagation Delay, Input A to Output Y (Figure 1) Input Capacitance 1.2 2.0 * 1.2 2.0 * 3.0 25C max 60 16 10 135 23 14 7.0 Guaranteed Limit -40C / 85C min max 75 20 13 405 28 18 -40C / 125C min max 90 24 15 405 34 21 pF ns Unit tPHL, (t PLH) CI CPD Power Dissipation Capacitance (Per Inverter) OA=25N, VI=0V/VCC pF 44 * - VCC= (3.30.3) V Used to determine the no-load dynamic power consumption: PD = CPDVCC2fI+ (CLVCC2fo), fI-input frequency, fo- output frequency (MHz) (CLVCC2fo) - sum of the outputs tHL 0.9 tL H 0.9 V1 0.1 0.1 V1 V CC Input A, B GND tP HL tP LH 0.9 0.9 V1 0.1 VC C Output Y 0.1 V1 tT LH tT HL GND V1 = 0.5 VC C Figure 1. Switching Waveforms VC C VI PULSE GENERATOR RT DEVICE UNDER TEST VO CL RL Termination resistance RT should be equal to ZOUT pulse generators Figure 2. Test Circuit SLS System Logic Semiconductor 4 |
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